Conventional processes used to form interconnect structures typically include a number of cycles of deposition of a patterning template (e.g., photoresist, hard mask, liner, or the like) followed by one or more etch processes. For example, a conventional process may include deposition of a masking layer followed by multiple etch processes to create features (e.g., trenches and vias) in an underlying layer disposed atop a substrate (e.g., a dielectric layer) to form an interconnect pattern. However, the inventors have observed that performing multiple etch processes may result in an uneven and non-uniform profile of the features in the interconnect pattern. In addition, the inventors have observed that the multiple etch processes may cause a degradation in the structural integrity of the features, undesirably resulting in a collapsing of the features during subsequent deposition processes (e.g., a metal fill).
Therefore, the inventors have provided an improved method for forming an interconnect pattern atop a substrate.